1. Field of the Invention
The present invention relates to the field of data transfer. More particularly, the present invention relates to an apparatus and method for packing data through addition in order to improve overall system performance.
2. Description of Art Related to the Invention
It is well known that computers systems as well as other "intelligent" systems include host memory. Typically, host memory includes a number of data buffers of an arbitrary byte size residing within a predetermined address range. These data buffers are uniquely addressed within the predetermined address range to allow selective access to the data stored within the data buffers for subsequent processing or transmission. Depending on the byte size of the data buffers and its byte availability, a block of data ("data block") may be written into one data buffer in a sequential manner, but is more likely fragmented into data blocks and non-sequentially written into more than one data buffer as shown in FIG. 1 in which, for example, forty (40) bytes of data are non-sequentially stored in three data buffers at starting data block addresses of 06H, 104H and 309H, where "H" indicates a hexadecimal address.
In the event that the data block needs to be transferred from host memory through a network system, it is usually desirable for each byte of the data block to be sequentially addressed (i.e., "byte packed"). This is normally accomplished by transferring the data block from host memory into an addressable, contiguous buffer. One primary reason for this type of byte packing is that networks usually transmit data in a continuous stream of data bytes to optimize performance. Thus, performance is degraded if the network is configured to transmit bytes containing invalid information.
Currently, a state machine is used to combine data from different data buffers into the single contiguous buffer if desired. A "state machine" is a collection of conventional logic or an Applied Specific Integrated Circuit ("ASIC") which receives inputs that are combined with its self-contained state information in order to "intelligently" control the combination of data from the different data buffers. However, the use of a state machine to control data combination poses a number of disadvantages.
One disadvantage is that this state machine is quite complex and thus, is difficult to design because it must account for every possible data buffer configuration having (i) any starting address within the predetermined address range and (ii) any arbitrary byte size. Another disadvantage is that a state machine is not modifiable (i.e., scalable) to accommodate data buffers supporting larger bit widths without dramatically altering the state machine and increasing its complexity. Thus, it would be desirous to provide an apparatus and corresponding method of operation that would overcome the above-identified disadvantages.